The present invention relates to a delay circuit whose delay time can be controlled, and, more particularly to a delay circuit used as one component of a line memory for use in a digital video apparatus such as a digital TV, a high-definition TV or a digital VCR.
FIG. 1 shows a conventional delay circuit whose delay time can be controlled. Input signal Din is supplied to first signal-delaying section 11, which is controlled by clock signals .phi. and .phi.. The output signal of signal-delaying section 11, or the delayed input signals Din, is supplied to second signal-delaying section 12 which is also controlled by clock signals .phi. and .phi.. The outputs of signal-delaying sections 11 and 12 are input to multiplexer 13. One of these outputs is selected by delay control signal DS supplied to multiplexer 13. Multiplexer 13 outputs the selected output from section 11 or 12, as a delayed output Dout. Hence, output Dout is delayed by the delay time of signal-delaying section 11 when multiplexer 13 selects the output of section 11, and delayed by the sum of the delay times of sections 11 and 12 when multiplexer 13 selects the output of section 12.
Signal-delaying sections 11 and 12 can be made of, for example, a dynamic shift register, as is shown in FIG. 2. This dynamic shift register comprises two clocked inverters 14 and 15. Clocked inverter 14 is controlled by clock signal .phi.. The output of clocked inverter 14 is input to clocked inverter 15. Clocked inverter 15 is controlled by clock signal .phi..
Alternatively, signal-delaying sections 11 and 12 can be comprised of such a static shift register as is shown in FIG. 3. This static shift register comprises four clocked inverters 16, 17, 18 and 19, and two inverters 20 and 21. Clocked inverters 16 and 19 are controlled by clock signal .phi.. Clocked inverters 17 and 18 are controlled by clock signal .phi..
The shift register shown in either FIG. 2 or FIG. 3 provides delay time equal to the one-cycle period of clock signal .phi.. Therefore, any desired number of circuits shown in FIG. 2, or any desired number of circuits shown in FIG. 3 can be connected in cascade and can thus be used as signal-delaying sections (like sections 11 and 12 of the circuit illustrated in FIG. 1), thereby to provide desired delay times.
The operation of the circuit shown in FIG. 1 will be explained with reference to the timing charts of FIGS. 4A and 4B. FIG. 4A shows how the circuit operates when signal-delaying section 11 comprises two shift registers of FIG. 2 or FIG. 3 to delay an input signal by the two-cycle period of clock signal .phi., and signal-delaying section 12 comprises one shift register of FIG. 2 or FIG. 3 to delay an input signal by the one-cycle period of clock signal .phi.. As is shown in this figure, when delay control signal DS is at the low level, the output of signal-delaying section 12 is selected. In this case, multiplexer 13 outputs delayed output Dout, or input signal Din which has been delayed by the three-cycle period of clock signal .phi.. Conversely, when delay control signal DS is at the high level, the output of signal-delaying section 11 is selected. In this case, multiplexer 13 outputs delayed output Dout, or input signal Din which has been delayed by the two-cycle period of clock signal .phi..
FIG. 4B shows how the circuit of FIG. 1 operates when signal-delaying section 11 is designed to delay an input signal by the four-cycle period of clock signal .phi., and signal-delaying section 12 is so designed as to delay an input signal by the two-cycle period of clock signal .phi.. When delay control signal DS is at the low level, the output of signal-delaying section 12 is selected, and multiplexer 13 outputs delayed output Dout, or input signal Din which has been delayed by the six-cycle period of clock signal .phi.. When delay control signal DS is at the high level, the output of signal-delaying section 11 is selected. In this case, multiplexer 13 outputs output signal Dout, or input signal Din which has been delayed by the four-cycle period of clock signal .phi..
FIG. 5 shows a delay control memory comprising three delay circuits 10-1, 10-2 and 10-3, all identical with the circuit of FIG. 1, one shift register 1, and n shift register, 2-1 to 2-n. Shift register 1 is used to synchronize input signal Din with a clock signal. Shift registers 2-1 to 2-n each store an input signal (Din) and then supply it to the next shift register. This memory has various delay times which are defined by various possible combinations of the two delay times of each delay circuit and one of which is selected in accordance with delay control signals DS1, DS2 and DS3.
Each of delay circuits 10-1 to 10-3, which constitute the delay control memory shown in FIG. 5, is provided with a multiplexer for selecting the output of one of the two signal-delaying sections forming the delay circuit. Each delay circuit, therefore, has many gates and many connecting wires. Since the delay control memory is comprised of some delay circuits of this type, which are connected in cascade, the memory will have a large chip size when it is manufactured in the form of an integrated circuit.